Recent projects:
Acceleration of bitnet on novel logical datapath
High speed serial i/o (clock extraction, oversampling)
Various audio projects (s/p dif, i2s, pcie, packet queuing, routing).
LLVM compiler for new Machine Learning Chip
Novel dataflow chip simulator
Backend placement and routing system for dataflow chip (a star algorithm + annealing)
Matlab library for DUC/DDC for comms
Logic design (mostly Verilog rtl with FPGA implementations):
ARM peripherals (SPI, watchdog, timers, real time control).
Power PPC interfaces and AES decryption. (Altera tools).
Processor design (16 bit 2 stage pipeline processor: alu, reg file, controller, interrupt controller, memory i/f, i/o, bus interface).
Verilog 2001, ISE Xilinx prototype emulated. 1st silicon on ASIC.
DSP (Matlab, Xilinx system generator) for wireless base stations.
Logic optimization:
Rewriting logic for self-timed micro-pipelines (logic co-factoring, logic re-encoding).
Physical logic optimization (Encoding logic decomposition alternates, choice network optimization, logic remapping during placement, SAT-sim optimizations)
Formal verification:
Formal logic verification (Fixed point algorithm implementation, support for constraint solver, linerarization, convergence).
Formal verification of timing exceptions
Formal verification of Clock Domain Crossings (CDC)
Older projects:
Logic processing system for Hybrid ASIC/FPGA:
(i) Logic restructuring (bdd based)
(ii)Verification (bdd compare)
(iii)Retiming and pipelining algorithms.
(iv)Lut mapper/packer (cut-map type with area recovery)
(v) HDL (Verilog) processing sub-system
(vi) Timing analysis sub-system.
Logic Design for high speed serial links:
VHDL Design self-id section of IEEE 1394phy b.
Infiniband Phy model (serdes, pll, 8b/10b enc/dec, elastic buffer, training machines, system C).
Optimization of lut-mapper (flowmap type algorithm) in commercial 3rd party EDA system.
Embedded design: one wire protocol for cell phone battery pack.
Logic synthesis engine for novel dsp.
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