/*
 * Copyright (c) 2008  RUSHC.
 * ------------------------
 *
 * 
 *
 * No warranty expressed or implied exists. Neither Rushc nor
 * Andy Fox provides any guarantees for the suitability of 
 * this code for any purpose. 
 *
 *
 * Module: 
 * Author: AF
 *
 * Feel free to send any bugs/queries about this code to
 *  andy@rushc.com
 * 
 */

#include <stdio.h>
#include <algorithm>
#include <map>
#include <set>
#include <vector>

/*
Interface to test the clock gating package
*/
int 
test_clockgate(std::vector<std::string> &verilog_source_files,
	       std::string &root_module,
	       bool verilog2k,
	       std::string& vin,
	       bool vin_w,
	       std::string& vout,
	       bool vout_w,
	       bool cg_ip,
	       bool cg_op
	       );
/*
Interface to test the abc verifier
*/
int test_verifyabc(std::string &fname1, std::string &fname2, std::string& root_module, bool verilog2k);

/*
Interface to test the generic abc interface
*/
int test_abcintf(std::string &abc_source_file,
		 std::vector<std::string> &verilog_source_files,
		 std::string &root_module,
		 bool verilog2k,
		 std::string& vin,
		 bool vin_w,
		 std::string& vout,
		 bool vout_w);

/*
Interface to test the logictools native verifier (works directly on verific data structures)
*/
int test_verify(std::string &fname1, std::string &fname2, std::string& root_module, bool verilog2k, std::string& vmode);


#include <boost/program_options.hpp>
namespace po = boost::program_options;
#include <iostream>
#include <iterator>
using namespace std;

int
main(int argc, char** argv){

  printf("------------------------------------------------------\n");
  printf("Demonstration program for logic tools\n");
  printf("Copyright RUSHC 2009. This binary contains\n");
  printf("trade secret information and should not be\n");
  printf("copied or distributed without written authorization\n");
  printf("General format: \n");
  printf("./logictools.exe --package [map,cgate,abc] -v <verilog source> -root <root module> -I <include directory> [-v2k] -k [Lut-size] \n");
  printf("For verification of 2 netlists:\n");
  printf("./logictools.exe --package [verify,abcdsec] -v1 <verilog source> -v2 <verilog source>  -root <root module> -I <include directory> [-v2k] \n");
  printf("------------------------------------------------------\n");

  /*
  The command line options
  */
  string cec_sec; 
  string root_module;
  string mode;
  string abc_script;
  string source_verilog_v1;
  string source_verilog_v2;
  bool cg_op;
  bool cg_ip;
  string vmode;
  bool vin_w=false;
  bool vout_w=false;
  string vin;
  string vout;
  std::vector<string> verilog_source_files;
  bool verilog2k=false;
 string abc_source_file;
  try {
  
    po::options_description desc("Allowed options");
    desc.add_options()
      ("help", "produce help message")
      ("package",po::value<string>(&mode) -> default_value("none"), "one of verify, map, cgate, abc, abcdsec")
      ("v",po::value<std::vector<string> >(&verilog_source_files), "verilog source files (map, cgate, abc)")
      ("v1",po::value<string>(&source_verilog_v1), "verify -- source file 1")
      ("v2",po::value<string>(&source_verilog_v2), "verify -- source file 2")
      ("vmode",po::value<string>(&cec_sec) -> default_value("cec"), "one of cec (combinational verification) sec (sequential verification)")
      ("root",po::value<string>(&root_module), "root module")
      ("I",po::value<std::vector<string> >(), "search directory for verilog")
      ("v2k",po::value<bool>(&verilog2k) -> default_value(true), "verilog 2k")
      ("abc_script",po::value<string>(&abc_source_file), "abc script")
      ("vin",po::value<string>(&vin), "output verilog on entry")
      ("vout",po::value<string>(&vout), "output verilog on exit")
      ("cg_op",po::value<bool>(&cg_op) -> default_value(false), "generate output-side enables for power savings")
      ("cg_ip",po::value<bool>(&cg_ip) -> default_value(true), "generate input-side enables for power savings")
      ;

    po::variables_map vm;
    po::store(po::parse_command_line(argc,argv,desc),vm);
    po::notify(vm);

    if (vm.count("help")) {
      cout << "Logic tools demonstration program. \n";
      cout << desc << "\n";
      return 1;
    }

    if (vm.count("vin"))
      vin_w = true;

    if (vm.count("vout"))
      vout_w = true;

  
    //run abc verification between 2 verific netlists.
    else if (mode == "abcdsec"){
      test_verifyabc(source_verilog_v1,source_verilog_v2,root_module,verilog2k);
      return 1;
    }

    //run verification natively on verific data structures (cec)
    else if (mode == "verify"){
      test_verify(source_verilog_v1,source_verilog_v2,root_module,verilog2k,cec_sec);
    }
    //run a generic abc script on verific netlist then exit.
    else if (mode == "abc"){
      test_abcintf(abc_source_file,verilog_source_files,root_module,verilog2k,vin,vin_w,vout,vout_w);
      return 1;
    }
    //run clock gating
    else if (mode == "cgate"){
      test_clockgate(verilog_source_files,root_module,verilog2k,vin,vin_w,vout,vout_w,cg_ip,cg_op);
      return 1;
    }
    else {
      cout << "Unknown package \n.";
      cout << desc << "\n";
      return 1;
    }
  }
  catch(exception& e){
    cerr << "error: " << e.what() << "\n";
    return 1;
  }
  catch (...){
    cerr << "Unknown type of exception \n";
  }


}