The Really Useful Software and Hardware Company (RUSHC)

RUSHC (Tel 831 621 0999   / / is a consulting company which does a mix of Hw and Sw projects. Typically projects begin with a fast prototype and initial version developed in the USA which is then passed to highly competent engineers in Armenia for further development. Our customers find this offers the benefits of high quality engineering with a good cost model -- the excellent Armenian engineering team typically quickly takes on the project offering long term capable engineering development (see images at the end of this page for a glimpse of our Armenian office). This model is ideal for startups where the requirement for high speed delivery of technically challenging tasks is met with formidable budget challenges.

What We Offer:

Unusually strong mix of logic design, compiler knowledge and algorithmic skills including:

  • Strong FPGA logic design skills. (Verilog, VHDL, Xilinx, Altera, Actel). Multiple FPGA projects eg SPI interfaces, movie projector sub-system. graphic system emulation. Recent experience with Accelerators using HLS (System C, C, Open CL) and SDx/SDAccel.

  • LLVM development capability (including both front end operations on LLVM IR and backend code generation).

  • Experience with processor, DSP, high speed serial, memory interface logic design.

  • IP core development.

  • Strong algorithmic knowledge and experience in logic Synthesis, Verification and Technology Mapper CAD tool development. Unusually strong in synthesis with complete synthesis systems developed for multiple clients, some published eg:  and

  • Embedded processor project development and debug

  • Exceptional C++ talent available for multiple projects.

Checkout some of our work !

Recently we have developed three interesting packages (mail to be added to git hub access list) including:
  1. Veriapps -- a package of chip design related algorithms working on verific netlists and using the UC Berkeley abc system. Includes formal verification of timing exceptions, lut mapping, asic mapping and a clean package for building abc structures from Verific netlists. Used extensively as a basis for EDA offerings by multiple clients.  paper:
  2. Powercompiler -- an llvm compiler flow for generating netlists of "Basic Block Processing Elements".
  3. Accelerators --In the  past we did some work on using High Level Synthesis for accelerator design -- basically an array of PE's specified using C/System C:  video:   We have recently been accelerating some interesting algorithms directly in Xilinx Ultrascale hardware using SDAccel and Vivado HLS. As well as further exploring and extending our PE arrays to best use the Xilinx UltraScale + architectures. Our accelerator work is being actively persued in Language and Logic Inc .

    Some documentation and other write ups on these projects can be found below. 

Document Library

DocumentLogic tools -- utilities for manipulating verific netlists. Documentation.Word Document. Logic tools is a package for manipulating Verific netlists including a source level hook up to abc (to get abc see:, various sat-sim utilities (verification, clock gate extraction) and lots of handy network manipulation functions all written in an easy to understand and maintain portable c++ style. No verific headers nor sources are included in this binary package so to use it you must first obtain a license (and they offer evaluation binary ones) from Verific.
Documentlogictools.zipZip of binary version of logictools library.
Documenttest_main.txtC++ sample of using logic tools library
DocumentAccelerators and HLSShort paper on using HLS for accelerator evaluation
Documenthls accelerator slidesSlides for notes on HLS and accelerators
Documentpowercompiler.pdfNotes on the power compiler (Basic Block PE generation)
DocumentveriappsVerific Applications using abc for formal verification, synthesis
Recent projects:

LLVM compiler for new Machine Learning Chip
Novel dataflow chip simulator
Backend placement and routing system for dataflow chip (a star algorithm + annealing)
Matlab library for DUC/DDC for comms
Logic design (mostly Verilog rtl with FPGA implementations):
ARM peripherals (SPI, watchdog, timers, real time control).
Power PPC interfaces and AES decryption. (Altera tools).
Processor design (16 bit 2 stage pipeline processor: alu, reg file, controller, interrupt controller, memory i/f, i/o, bus interface).
Verilog 2001, ISE Xilinx prototype emulated. 1st silicon on ASIC.
DSP (Matlab, Xilinx system generator) for wireless base stations.

Logic optimization:
Rewriting logic for self-timed micro-pipelines (logic co-factoring, logic re-encoding).

Physical logic optimization (Encoding logic decomposition alternates, choice network optimization, logic remapping during placement, SAT-sim optimizations)

Formal verification:
Formal logic verification (Fixed point algorithm implementation, support for constraint solver, linerarization, convergence).
Formal verification of timing exceptions
Formal verification of Clock Domain Crossings (CDC)

Older projects:

Logic processing system for Hybrid ASIC/FPGA:
(i) Logic restructuring (bdd based)
(ii)Verification (bdd compare)
(iii)Retiming and pipelining algorithms.
(iv)Lut mapper/packer (cut-map type with area recovery)
(v) HDL (Verilog) processing sub-system
(vi) Timing analysis sub-system.

Logic Design for high speed serial links:
VHDL Design self-id section of IEEE 1394phy b.
Infiniband Phy model (serdes, pll, 8b/10b enc/dec, elastic buffer, training machines, system C).

Optimization of lut-mapper (flowmap type algorithm) in commercial 3rd party EDA system.

Embedded design: one wire protocol for cell phone battery pack.

Logic synthesis engine for novel dsp.

Even older projects:

Verilog Designs (packer queue, cam, Banyan Batcher sorting network)
Chip verification (Symbolic simulation and debug of novel DSP)
RTL processing sub-system (for reconfigurable computing chip)
Technology mappers (4 commercial including: Lut -based, ECL, Mux based, Reed-Muller xor tree mapper)
Hardware emulation (Flat panel controller model)
VHDL macro design.

For more information e-mail and see